1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a structure of a DMOS type (Diffused Mos-type) high voltage transistor and a method of manufacturing the same.
2. Description of the Related Art
A high voltage MOS transistor has a high source/drain breakdown voltage or a high gate breakdown voltage and is generally used for various drivers such as an LCD driver, a power supply circuit or the like. In recent years, there has been a need particularly for a high voltage MOS transistor having a high source/drain breakdown voltage Bvds and a low on-resistance.
FIG. 19 shows a structure of a conventional P-channel type high voltage MOS transistor (hereafter, referred to as a conventional HV-PchMOS). An N-type epitaxial semiconductor layer 51 is formed on a P-type single crystal semiconductor substrate 50 by epitaxial growth, and an N+-type embedded semiconductor layer 52 is formed at an interface of the single crystal semiconductor substrate 50 and the epitaxial semiconductor layer 51. A gate electrode 54 is formed on the epitaxial semiconductor layer 51 with a gate insulation film 53 being interposed therebetween. A P+-type source layer (PSD) 55 is formed on the right side of the gate electrode 54, and an N-type well layer (N+W) 56 extends from the source layer 55 side to under the gate electrode 54.
A P-type drift layer 57 is formed on the left side of the gate electrode 54, and the right 25 end of the layer 57 extends under the gate electrode 54. A surface region of the N-type well layer 56 between this drift layer 57 and the source layer 55 serves as a channel region CH1, and the length of this channel region CH1 is an effective channel length Leff1. The drift layer 57 is a region where carriers drift, and also serves to reduce a drain electric field by depletion when a high voltage (in this case, a negative high voltage relative to the source layer 55) is applied to a 30 drain layer 58.
The P-type drain layer 58 is formed on the left side of the drift layer 57, being in contact with this drift layer 57. The drain layer 58 is made of three P-type layers (a PSD layer, a SP+D layer, and a P+D layer), in which the PSD layer on the surface has the highest concentration, the SP+D layer thereunder has the second highest concentration and the P+D layer thereunder has the lowest concentration. Providing the drain layer 58 with such concentration gradient increases the expansion of a depletion layer of the drain layer 58, contributing to realization of a higher voltage MOS transistor.
Furthermore, a first field plate 60 extending from above a portion of the gate electrode 54 onto the drift layer 57 with a first interlayer insulation film 59 being interposed therebetween and a second field plate 62 extending from above a portion of the first field plate 60 onto the drift layer 57 with a second interlayer insulation film 61 being interposed therebetween are formed. The first and second field plates 60 and 62 are set to the same potential as that of the source layer 55. The first and second field plates 60 and 62 serve to expand the depletion layer of the drift layer 57 and reduce the drain electric field. The high voltage MOS transistor is disclosed in the Japanese Patent Application Publication No. 2004-39774.